Exemplary embodiments of the present invention relate to an internal command generation device.
A semiconductor memory device receives an external voltage (VDD) and a ground voltage (VSS) and converts the received external voltage (VDD) and ground voltage (VSS) into internal voltages necessary for internal operations. Examples of the internal voltages necessary for the internal operations of the semiconductor device include a core voltage (VCORE) supplied to a core region, a high voltage (VPP) supplied for driving a word line, a cell plate voltage (VCP) supplied to a plate electrode of a capacitor, and a bit line precharge voltage (VBLP) supplied to a bit line pair BL and BLB during a precharge operation.
When a semiconductor memory device enters a power-up mode (power ramp sequence), an internal voltage rises until it reaches a predetermined level along a level of an external voltage (VDD). Thus, a process of stabilizing an internal voltage is required before the start of a normal operation such as a read or write operation. The stabilization of the internal voltage is achieved through the continuous use of the internal voltage. Therefore, a typical SDRAM stabilizes an internal voltage by performing a refresh operation in response to the input of an external refresh command.
Meanwhile, as described in the specification, an LPDDR2 RAM receives an external reset command and sets a device auto initialization period of approximately 10 μs after entering a reset state. Like an SDRAM, no refresh command is inputted in the device auto initialization of the LPDDR2 RAM. Consequently, there is no way to stabilize the internal voltage.